15 Commits

Author	SHA1	Message	Date
Robin Dietzel	51cdb6966d	Finished base design	2023-02-02 18:05:58 +01:00
Robin Dietzel	e86a424de2	Connected all nets	2023-02-02 18:05:58 +01:00
Robin Dietzel	f48bf3d3b9	Created GND planes	2023-02-02 18:05:58 +01:00
Robin Dietzel	5eb3848e16	Finished all supply signals except gnd	2023-02-02 18:05:58 +01:00
Robin Dietzel	bfa44d9373	Finished basic signal routing	2023-02-02 18:05:58 +01:00
Robin Dietzel	9d0fd02eed	More PCB layout	2023-02-02 18:05:58 +01:00
Robin Dietzel	adfd4636af	More Layout	2023-02-02 18:05:58 +01:00
Robin Dietzel	29932669a3	Corrected placement of screw terminals	2023-02-02 18:05:58 +01:00
Robin Dietzel	77f4c3725c	More PCB layouting	2023-02-02 18:05:58 +01:00
Robin Dietzel	37c6003558	Started PCB Layouting	2023-02-02 18:05:58 +01:00
Robin Dietzel	2d3170f32a	Tweaked schematics	2023-02-02 18:05:58 +01:00
Robin Dietzel	8dad08981e	CLEANUP: cleaned up design and named testpoints	2023-02-02 18:05:58 +01:00
Robin Dietzel	843bd42a06	FEATURE: added additional footprints	2023-02-02 18:05:58 +01:00
Robin Dietzel	aaba0fe2cc	FEATURE: linked JLCPCB Parts and assigned many footprints	2023-02-02 18:05:58 +01:00
Robin Dietzel	151f2b39dd	FEATURES: added complete input and output channels	2023-02-02 18:05:58 +01:00